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ADT7467
Table 80. REGISTER 0X78 ? CONFIGURATION REGISTER 3 (POWER-ON DEFAULT = 0X00)
Bit
<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
Name
ALERT
Enable
THERM
BOOST
FAST
DC1
DC2
DC3
DC4
R/W (Note 1)
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
ALERT = 1, Pin 5 (PWM2/SMBALERT) is configured as an SMBALERT interrupt output to
indicate out-of-limit error conditions.
THERM Enable = 1 enables THERM timer monitoring functionality on Pin 9. Also determined
by Bit 0 and Bit 1 (Pin 9 Func) of Configuration Register 4. When THERM is asserted, the fans
run at full speed if the fans are running and the boost bit is set. Alternatively, THERM can be
programmed so that a timer is triggered to time how long THERM has been asserted.
When THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the
maximum programmed duty cycle for fail-safe cooling.
FAST = 1 enables fast TACH measurements on all channels. This increases the TACH
measurement rate from once per second to once every 250 ms (4 ? ).
DC1 = 1 enables TACH measurements to be continuously made on TACH1. Fans must be
driven by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven
motors.
DC2 = 1 enables TACH measurements to be continuously made on TACH2. Fans must be
driven by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven
motors.
DC = 1 enables TACH measurements to be continuously made on TACH3. Fans must be
driven by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven
motors.
DC4 = 1 enables TACH measurements to be continuously made on TACH4. Fans must be
driven by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven
motors.
1. This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this
register fail.
Table 81. REGISTER 0 X79 ? THERM TIMER STATUS REGISTER (POWER-ON DEFAULT = 0X00)
Bit
<7:1>
<0>
Name
TMR
ASRT/TMR0
R/W
Read Only
Read Only
Description
Times how long THERM input is asserted. These seven bits read 0 until the THERM asser-
tion time exceeds 45.52 ms.
This bit is set high upon the assertion of the THERM input and is cleared upon a read. If the
THERM assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8-bit
TMR reading. This allows THERM assertion times from 45.52 ms to 5.82 sec to be reported
back with a resolution of 22.76 ms.
Table 82. REGISTER 0 X7A ? THERM TIMER LIMIT REGISTER (POWER-ON DEFAULT = 0X00)
Bit
<7:0>
Name
LIMT
R/W
Read/Write
Description
Sets the maximum THERM assertion length before an interrupt is generated. This is an
8-bit limit with a resolution of 22.76 ms, allowing THERM assertion limits of 45.52 ms to
5.82 sec to be programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P) of
Interrupt Status Register 2 (0x42) is set. If the limit value is 0x00, an interrupt is generated
immediately upon the assertion of the THERM input.
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